In the microscopic world of semiconductor manufacturing, etching is like nanoscale carving. Its core function is to accurately reproduce the pattern transferred by lithography onto the substrate material by selectively removing unnecessary regions. Etching creates nanoscale structures with high aspect ratios and small dimensional errors and is a key process for chips, 3D NAND and other devices. From linewidths one-thousandth the width of a human hair to microchannels with aspect ratios above 100:1, this precision depends on the coordination of physical and chemical mechanisms and meticulous control of process parameters.
Etching processes are mainly divided into wet etching and dry etching, each suited to different nanoscale carving needs. Wet etching is a purely chemical reaction process. It uses etchants that react specifically with target materials to remove unprotected regions. It has advantages such as simple equipment, low cost and good selectivity. For example, potassium hydroxide can etch silicon wafers by using the different etch rates of crystal planes to create V-groove structures in MEMS devices. However, wet etching causes serious lateral undercutting and cannot meet the high-precision requirements of processes below 7 nm, so it is gradually used as an auxiliary process.
Dry etching is the mainstream method for nanoscale carving today, with plasma etching as the representative technology. It combines physical bombardment and chemical reaction to achieve precise and controllable material removal. In a vacuum reaction chamber, RF power excites process gases into plasma containing ions and radicals. High-energy ions bombard the material surface like carving tools, while radicals react with the material to generate volatile products that are pumped away. This method provides strong anisotropy and can form steep sidewalls. When combined with pulsed plasma technology, it enables microsecond-level energy control and balances etching rate with structural integrity.
Precise carving of nanoscale structures requires overcoming three major control challenges. First, process parameters such as gas ratio, RF power and chamber pressure must be tightly matched. For silicon etching, adjusting the chlorine and nitrogen ratio can help control the sidewall angle close to 90 degrees; in 3D NAND etching, RF power must be significantly increased to address high-aspect-ratio requirements. Second, endpoint detection must be accurate. Monitoring plasma spectra or reaction product concentrations helps prevent over-etching that damages underlying layers or under-etching that leaves incomplete patterns. Third, defects must be suppressed. Low-temperature etching can freeze by-products to form sidewall protection layers, reducing channel bending and residue accumulation.
Today, etching precision has reached the atomic scale, and advanced etching equipment can achieve extremely fine process control. From carving trillions of storage holes in 3D NAND to fabricating transistors in 5 nm chips, etching precision directly affects device performance and storage capacity. As process nodes continue toward 3 nm and below, etching will further integrate multiple technologies to achieve more precise carving at smaller scales and provide core support for semiconductor industry development.
