In the micro/nano world of semiconductor and MEMS manufacturing, patterning is the core battlefield that determines device precision and performance. Lithography and etching work like a “drafter” and a “carver”: the former accurately reproduces the design blueprint, while the latter faithfully sculpts the physical structure. Together, they transform macroscopic design into nanoscale devices and build the foundation of modern electronics.
As the first move in patterning, lithography transfers circuit patterns from the photomask onto the photoresist on the wafer surface. The process resembles nanoscale photography. After cleaning and pretreatment, the wafer is coated with a uniform photoresist layer, followed by soft baking to remove solvent and improve adhesion. The lithography machine then uses a specific wavelength, from deep ultraviolet (DUV) to extreme ultraviolet (EUV), to expose the mask pattern onto the photoresist. The exposure triggers photochemical reactions that change local solubility. After development, unprotected resist is dissolved to form a temporary pattern template. A post-bake step further improves the template’s resistance to etching.
The technical bottlenecks of lithography lie in resolution and alignment control. EUV lithography, with its short wavelength, can achieve pattern transfer for line widths below 3 nm. Overlay accuracy determines the matching of multiple device layers and is a key factor affecting chip integration density.
If lithography creates the template, etching creates the real structure. Through selective material removal, etching permanently transfers the temporary resist pattern into the wafer substrate. This subtractive process is divided into wet etching and dry etching. Wet etching uses chemical solutions to dissolve target materials. It is low-cost and easy to operate, but has poor anisotropy and is prone to lateral undercutting, so it is mainly used in mature processes above 28 nm. Dry etching uses plasma as the core carving tool and removes material through both ion bombardment and chemical reaction. Its precision can reach the nanoscale and it accounts for most modern etching processes.
The technical core of dry etching is precise control. Capacitive coupled plasma (CCP) and inductively coupled plasma (ICP) etching each have their strengths. CCP is suitable for hard dielectric materials, while ICP, with high-density plasma, can process materials such as single-crystal silicon more effectively. In 3D NAND manufacturing, etching must address aspect ratios as high as 70:1, while keeping countless tiny vias parallel and uniform. Process difficulty rises sharply with the number of stacked layers and places high demands on equipment stability.
The coordination between lithography and etching directly determines device yield. Lithography sets the resolution limit, while etching selectivity and uniformity determine pattern fidelity. If etch rate is uneven or sidewalls tilt, even the most precise lithography pattern can fail to be faithfully transferred. As process nodes move toward 2 nm, the number of etching steps per chip can reach hundreds, and etching cost may account for 15%–20% of total process cost, making it the second major cost item after lithography.
From laboratories to production lines, lithography and etching continue to evolve together. Breakthroughs in etching equipment and continuous advances in lithography drive micro/nano fabrication toward smaller dimensions and higher precision. This patterning battle is not only a competition of equipment and materials, but also a test of process integration. Its progress will unlock more possibilities in the microscopic world.
