As the semiconductor industry moves toward higher density, higher performance and lower power consumption, the integration of silicon wafers with SOI (silicon-on-insulator) wafers has become critical for breaking through performance bottlenecks. SOI wafers are widely used in high-end chips because their insulating layer reduces leakage current and parasitic capacitance. Atomic-level bonding—meaning a gap-free, impurity-free interface where atoms are tightly connected through chemical bonds—is the prerequisite for unlocking these advantages and directly determines the upper limit of chip performance. This article reviews mainstream bonding technologies and explains the principles, process points and industrial applications behind atomic-level bonding between silicon and SOI wafers.
To achieve atomic-level integration, it is necessary to understand the structures and key requirements of the two substrates. A standard silicon wafer is mainly single-crystal silicon with a natural oxide layer on the surface. An SOI wafer consists of a top silicon layer, a buried oxide layer (SiO₂) and a silicon handle substrate. Bonding mainly occurs between the silicon wafer and the top silicon or handle silicon of the SOI wafer. The key is to ensure interface strength without damaging the buried insulation layer. Current mainstream bonding technologies include direct bonding and hybrid bonding. Silicon-to-silicon direct bonding (SDB) is widely used, while hybrid bonding is better suited to advanced applications.
Silicon-to-silicon direct bonding is a foundational technology. Its principle is to form active surface groups through surface treatment and then create covalent atomic bonding under pressure and temperature, without an intermediate layer. The key lies in surface pretreatment and annealing. Chemical mechanical polishing (CMP) is first used to control surface roughness below 0.5 nm. RCA cleaning then removes contaminants and oxide residues. Plasma activation generates dangling bonds and hydroxyl groups on the silicon surface, creating the conditions required for bonding.
After pretreatment, the two substrates are brought into contact at room temperature and initially held together by van der Waals forces. Annealing then increases the bonding strength step by step. At 200–400°C, hydroxyl groups form silanol bonds. Above 800°C, silanol bonds polymerize into stable Si-O-Si bonds while water molecules are expelled. Above 1000°C, complete covalent bonding can be achieved, with bonding strength reaching more than 80% of single-crystal silicon. This technology offers high interface purity and strong compatibility, and is widely used in SOI wafers and MEMS devices, but it requires extremely high surface flatness and cleanliness.
As chips move toward three-dimensional integration, hybrid bonding has become an advanced solution. It combines the advantages of dielectric bonding and metal bonding. Copper-to-copper hybrid bonding is one of the most widely used approaches, enabling both dielectric layer fusion, such as SiO₂ bonding, and direct copper interconnection. It provides mechanical strength and electrical connectivity at the same time, overcoming limitations of traditional direct bonding.
The copper-to-copper hybrid bonding process is more complex. Copper pads and dielectric layers are first fabricated, and CMP is used to control copper surface roughness below 1 nm and dielectric roughness below 0.5 nm. After surface activation removes oxides and contaminants, the wafers are precisely aligned and bonded. Under a temperature of 200–300°C and high pressure, dielectric fusion and copper atom diffusion bonding occur. Interconnect density can reach 17,500 to 1,000,000 I/O per mm², with pitch reduced to 0.1–0.5 μm, making the process suitable for HBM memory, 3D NAND and other high-end applications.
Anodic bonding and low-temperature bonding are also used in specific scenarios. Anodic bonding drives ion migration in the oxide layer through a high-voltage electric field and is suitable for MEMS vacuum packaging. Low-temperature bonding reduces the bonding temperature below 200°C, helping avoid damage to the SOI buried layer and making it suitable for temperature-sensitive chips. Its bonding strength is slightly lower, so process optimization is needed to compensate.
Atomic-level bonding must overcome three major challenges. The first is surface quality control: particles larger than 0.1 μm or abnormal surface morphology can cause bonding voids. The second is alignment accuracy: advanced bonding requires alignment error below 1 μm. The third is thermal stress control: the process must be optimized to reduce warpage caused by differences in thermal expansion between the silicon wafer and the SOI wafer.
Overall, atomic-level bonding between silicon wafers and SOI wafers is a core support technology for advanced chip manufacturing. Direct bonding, hybrid bonding and related technologies cover different application requirements. Every improvement from surface pretreatment to annealing optimization drives technology iteration and will continue to provide essential support for future chip performance breakthroughs.
